编码器 VHDL - 验证和模型模拟

此模块必须确保当编码器旋转时，它将计算已执行的编码器步骤数。如果编码器顺时针旋转，模块必须加一步，逆时针减一步。该模块是基于状态机设计的，也用于vhdl代码中。

有人能验证我的编码器代码吗？我如何在modelsim中验证我的代码？

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;



entity ENCODER is
Port (SYS_CLK: in STD_LOGIC;
A: in STD_LOGIC;
B: in STD_LOGIC;
RST: in STD_LOGIC;
POSITION: out STD_LOGIC_VECTOR(15 downto 0);
ENC_ERROR: out STD_LOGIC);
end ENCODER;



Architecture Behavioral of ENCODER is
signal POSI: integer;



Begin
PROCESS (RST, SYS_CLK, A, B)

Begin
if RST = '0' AND rising_edge(SYS_CLK) then
if (A>B) then
POSI <= POSI + 1;
end if;
end if;
if RST = '0' AND rising_edge(SYS_CLK) then
if (B>A) then
POSI <= POSI - 1;
end if;
end if;

if RST = '1' then
POSITION <= "0000000000000000";
end if;

POSITION <= std_logic_vector(to_unsigned(POSI, POSITION'length));

end PROCESS;
end Behavioral;